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Often, and certainly in the early stages of a design, the knowledge about delays is imprecise. Stochastic programming is not an adequate means to account for this imprecision. Not only is a probability distribution seldom a correct translation of the designer's delay knowledge, it also leads to inefficient algorithms. In this paper possibilistic programming is proposed for handling the retiming problem...
Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel path-based algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have been...
In this paper we summarize the derivation of the size equations, the key to timing closure, which is the dimensioning of a logic network such that timing constraints are satisfied. Next we present a number of problems when applying these equations in practice. The main ones are network generation, discrete libraries, size constraints, and resistive interconnect.
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