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A 2.2 GS/S 4??-interleaved 6b ADC in 40 nm digital CMOS is presented. Each ADC slice consists of a 1b folding stage followed by a pipelined binary-search sub-ADC using dynamic nonlinear amplifiers for low power consumption and high speed. Threshold calibration corrects for amplifier and comparator imperfections and 31.6 dB SNDR is achieved with 2 GHz ERBW for 2.6 mW power consumption.
A solid-state three-dimensional Time-of-Flight sensor is presented consisting of 32 times 32 range pixels based on Current-Assisted Photonic Demodulation (CAPD). Each pixel measures 30 mum times 30 mum and consists of 6 transistors and a differential current-assisted photonic demodulator, yielding a Fill-Factor of 66%. The sensor is implemented in 0.35 m standard CMOS technology without optical optimization...
A 5 bit 1.75 GS/s flash ADC is realized in 90 nm CMOS. It uses a comparator array with built-in imbalance and offset calibration to lower power consumption. The SNDR is 30.9 dB at low frequencies and gradually degrades to 28.2 dB at 2 GHz. The ADC occupies 280 mum by 110 mum and draws only 7.6 mA from a 1 V supply yielding an energy efficiency of 0.15 pJ/conversion step.
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