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A data-centric network architecture, Named Data Networking (NDN) has been developed to meet applications' growing demands of network effciency and resilience. Currently, the deployment of NDN in real network environments requires careful system design to not only enable NDN but also support IP traffc, considering IP network has been prevalent for decades and almost all the equipments and applications...
Deep convolutional neural networks (CNNs) are widely adopted in intelligent systems with unprecedented accuracy but at the cost of a substantial amount of data movement. Although recent development in processing-in-memory (PIM) architecture seeks to minimize data movement by computing the data at the dedicated nonvolatile device, how to jointly explore the computation capability of PIM and utilize...
Sensitive data are usually transferred within a vehicle using FlexRay protocol. To prevent the in-vehicle data from the manipulation and man-in-the-middle attacks through On Board Diagnostic (OBD-II) port, appropriate security schemes should be applied. In this paper, we propose a scheme to embed data integrity and confidentiality into the original FlexRay data frames and reuse the Cyclic Redundancy...
There are many simulators to evaluate the performance of computer architecture, however they are commonly based on Software Architecture Model Execution (SAME). Due to hardly implement parallel execution on multicore platforms, their simulation speeds are slow. To solve the problem, we propose to improve simulation speed of SAME simulators on FPGA using SystemC synthesizable timing models. First,...
The OpenFlow paradigm embraces third-party development efforts, and therefore suffers from potential attacks that usurp the excessive privileges of control plane applications (apps). Such privilege abuse could lead to various attacks impacting the entire administrative domain. In this paper, we present SDNShield, a permission control system that helps network administrators to express and enforce...
Three-dimensional (3-D) NAND flash technology has been attracting much attention in recent years, for it overcomes the challenges of scaling limitation faced by 2-D NAND flash and meets the demand of higher storage density and lower bit cost. Several 3-D NAND flash architectures has been proposed recently. [1-3] However, most of these structures have adopted poly-crystalline silicon (poly-Si) as the...
Storage class memory (SCM) modules can be placed side-by-side with DRAM on the memory bus, available to memory instructions issued by the CPU. This shift engenders a new “DRAM-SCM” storage architecture and potentially allows near-DRAM secondary storage access speed, which is several orders of magnitude faster than magnetic disk or flash memory. Utilizing SCM as a secondary storage device will have...
Driven by the requirements from traffic volume versatile services and spectrum scarcity, the concept of cloud network and cognitive radio could become new features in the next generation mobile and wireless access networks. For example, to deploy LTE femtocells and Wi-Fi networks in the TV white spaces provides a new way for traffic offloading and enables spectrum sharing as a cognitive radio network...
Due to the variable garbage collection latency, NAND flash memory storage systems may suffer long system response time, especially when the flash memory is close to be full. Most of existing flash translation layer (FTL) schemes focus on improving the average response time but ignore to provide a desirable worst case response time upper bound. This paper proposes a Real-time Flash Translation Layer...
In the recent years, embedded systems began to be used in sensitive applications such as personal digital assistants and smart cards. Due to very strict cost and power constrains, the support for cryptography provided by these devices is often limited to either public or private key primitives. This limitation is much more evident in devices where the cryptographic algorithms are implemented using...
With the fast development of mobile computing, m-learning which makes anyone to learn in anytime and anywhere by any methods of learning, gains more attention and has been used widely. After studying the domestic and international research and development condition of m-learning, this paper presents the system architecture of mobile digital campus based on 3G, combined with the characteristics and...
The increasing capacity of NAND flash memory leads to large RAM footprint on address mapping in the Flash Translation Layer (FTL) design. The demand-based approach can reduce the RAM footprint, but extra address translation overhead is also introduced which may degrade the system performance. This paper proposes a two-level caching mechanism to selectively cache the on-demand page-level address mappings...
Regular expression (Regex) becomes the standard signature language for security and application detection. Deterministic finite automata (DFAs) are widely used to perform regex matching in linear time. Previously researches mostly focus on how to compress DFA to reduce memory requirements in recent years. However, memory requirement is not the only problem caused by DFA explosion when implementation...
In this paper, we focus on solving the problem of removing inter-core communication overhead for streaming applications on chip multiprocessors. The objective is to totally remove inter-core communication overhead while minimizing the overall memory usage. By totally removing inter-core communication overhead, a shorter period can be applied and system throughput can be improved. Our basic idea is...
In this paper, we jointly optimize computation and communication task scheduling for streaming applications on MPSoC. The objective is to minimize schedule length by totally removing inter-core communication overhead. By minimizing schedule length, the system performance can be improved by adopting a smaller period or exploring the slacks generated for energy reduction with DVS. To guarantee the schedulability...
The shading processors in graphics hardware are becoming increasingly general-purpose. We test, through simulation and benchmarking, the potential performance impact of replacing these processors with a fully general-purpose parallel processor, without the fixed-function graphics hardware legacy of current graphics processing units (GPUs). The representative general-purpose processor we test against...
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