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High-k gate stack reliability has become one of the critical factors impacting the introduction of advanced gate stacks in future technology nodes. A high density of as-grown electron traps in the transition metal oxides (Bersuker et al., 2004) and the presence of the SiO2 layer at the interface between the high-k dielectric and the substrate, complicate evaluation of stress-induced defect generation...
We report on the relationship between the materials science of a HfO2/TiN stack and transistor performance. Atomic layer deposited (ALD) HfO2 can be scaled to a physical thickness of 1.2 nm resulting in EOT 1.0 nm. In scaling HfO2 the interfacial SiO2 layer (IL) is also scaled and the extent of HfO2 crystallization is reduced. Reduced HfO2 crystallinity is coincident with reduced threshold voltage...
The impact of nitrogen on charge trapping induced positive bias temperature instability (PBTI) characteristics in HfSiON/TiN gate stacks is investigated. While thickness is found to be the primary parameter to reduce charge trapping, plasma nitrogen reduces PBTI effects in thick (2.7 nm) HfSiON films. Thin films (1.8 nm) show significantly lower threshold voltage (VTH) shift than thick films and seem...
Positive constant voltage stress combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO2 /HfO2/TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-k gate...
Positive bias constant voltage stress combined with charge pumping (CP) measurements were applied to study trap generation phenomena in SiO 2/HfO2/TiN stacks. Using gate stacks with varying thicknesses of the interfacial SiO2 layer (IL) or high-kappa layer and analysis for frequency-dependent CP data developed to address trap depth profiling, the authors have determined that the defect generation...
Constant voltage stress (CVS) combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO2 /HfO2/TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-k gate stacks...
We show an ALD based HfSiON gate dielectric scaled to 1 nm EOT with excellent performance and reliability. Furthermore, the HfSiON dielectric films are integrated in a gate first approach that includes a 1000degC-5s anneal. It is also demonstrated that this 1 nm EOT HfSiON can achieve electron and hole mobilities comparable to that of SiON. This progress is enabled due to better understanding of the...
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