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A low power design of CMOS bandgap reference of current mode used in analog-to-digital converter is proposed to obtain stable reference current and voltage. It realizes low power by one-order temperature compensation, resistance startup block, optimized internal operational amplifier and a new designed reference voltage buffer instead of closed loop. Under SMIC CMOS 0.35um 1P6M process and simulated...
This paper presents a sigma-delta modulator of two-order with switched-capacitors (SC) techniques for low power in 0.18 um CMOS process. Without continues current transmission SC techniques present a discrete low power system. And a low power op amplifier with discrete common-mode feedback and a dynamic comparator is also designed. This new amp works under the supply of 1.8 v and with the direct current...
A pipelined ADC using shared amplifiers in two-channel time-interleaved design is proposed. The two channels have a unify sample and hold amplifier. In the time-interleaved pipelined part, the large mismatch between the channels is reduced by the shared amplifier in the same stage. And power consumption and chip area also been decreased. Under SMIC 0.35um 1P6M CMOS process with 3.3V supply, the SNR...
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