The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper we report experimental results on the fabrication and characterization of vertical Ge gate-all-around p-channel TFETs, utilizing GeSn as a channel material. Through two sample series, the potential and challenges of implementing the low-band gap material GeSn are reviewed. It is verified that ION can be effectively enhanced by increasing the Sn-content in the GeSn-channel, due to increasing...
This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676mum2 and 0.54mum 2 SRAM cells, optimized for performance and density, respectively. The key focus of this technology has been low cost, process simplicity and...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.