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The design of a 4× blind analogue-to-digital converter (ADC)-based receiver implemented in 65 nm CMOS technology is presented. The ADC, which has three levels with two adjustable thresholds, effectively implements a speculative decision-feedback equaliser. By reducing the ADC resolution and by simplifying the digital clock and data recovery design, the power consumption is reduced by a factor of 2...
ADC-based receivers allow for extensive equalization in the digital domain and therefore can easily compensate for channel loss at higher data rates. Digital equalization can be implemented as an FFE or DFE. An adaptive FFE is straight forward to implement, as it relies on magnitudes only (not phases) of the blind samples, however, it enhances the quantization noise of the ADC. A DFE has better noise...
This paper presents a fractional-sampling-rate (FSR) CDR that blindly samples the received signal with an ADC at 1.45x the data rate and estimates the data phase using a feedforward architecture for clock and data recovery. The presented architecture reduces the ADC power by 27.3% compared to a 2x CDR. Measurements confirm that the FSR CDR recovers data with BER<1013 at 6.875 Gb/s from samples...
An SSC-compliant 5 Gb/s transceiver in 65 nm CMOS is developed and tested. The receiver uses an ADC-based front-end that samples the incoming signal without adjusting the phase difference between the sampling clock and the signal. The phase tracking of the input signal and the data decision are performed entirely in the numerical domain.
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