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Verifying digital control programs for a complicated power electronic system is usually time consuming. In this paper, a circuit simulation method to verify digital control programs is investigated. This method uses the C block provided by PSIM to integrate digital control program code into the circuit simulation environment. A program module packaging technique is first exploited to guarantee the...
The energy efficiency of network hardware has become a topic of considerable interest in recent years, motivated by the explosive growth of information and communication technology (ICT), and the ever increasing energy costs as well as the need to reduce Greenhouse Gas (GHG) emissions globally. One approach to saving energy in routers is to use dynamic adaptation, and this paper describes the development...
Recently, energy expenditures of the Internet have increased dramatically, raising energy issue of routers an urgent problem in relative research areas. In fact, much device surplus and redundancy are introduced during network planning for rarely appeared traffic peak hours and device failures, wasting energy most of the time. In this work, an energy-aware architecture is proposed for routers, which...
This paper presents radix-4 and radix-8 Booth encoded modular multipliers over general Fp based on inter-leaved multiplication algorithm. An existing bit serial interleaved multiplication algorithm is modified using radix-4, radix-8 and Booth recoding techniques. The modified radix-4 and radix-8 versions of interleaved multiplication result in 50% and 75% reduction in required number of clock cycles...
In this paper, we propose an efficient 256×256 bit modular multiplier based on Montgomery reduction algorithm. The 256 × 256 bit modular multiplier is required in elliptic curve and pairing based cryptographic protocols to achieve 128 bit security level. The in-built features of modern FPGA are efficiently utilized. Two time consuming components (1) 512-bit addition (2) 256 × 256 bit multiplier are...
Deep Packet Inspection (DPI) involves searching a packet's header and payload against thousands of rules to detect possible attacks. The increase in Internet usage and growing number of attacks which must be searched for has meant hardware acceleration has become essential in the prevention of DPI becoming a bottleneck to a network if used on an edge or core router. In this paper we present a new...
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