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This paper proposes a reconfigurable, spectrally efficient 7-tap FIR pulse based UWB transmitter with the maximum pulse rate of 1.6Gpulses/s. By utilizing a Δ-Σ PLL and a DAC embedded FIR pulse generator, digitally configurable pulse generation is done with high spectral efficiency. For low power 7-tap FIR pulse generation, a 1/8-rate, 16-phase injection-locked oscillator (ILO) is designed instead...
A semi-digital PLL utilizing a hybrid DCO is presented. A mixed-mode loop control with an analog proportional path and a digital integration path provides linear phase tracking, leakage-insensitive loop filtering, and technology scalability. With the absence of the linear TDC, the semi-digital PLL with the hybrid DCO can relax design difficulties such as achieving low power or requiring an advanced...
This paper describes a quantization noise reduction method for ΔΣ based digitally-controlled ring oscillators (DCRO). A concept of the hybrid finite-impulse response (FIR) filter from the fractional-N PLL is extended to the DCRO design. Thanks to the parallel operation, the proposed filter based noise reduction method does not cause any additional latency to the digital PLL. Both behavioral and circuit-level...
A 3.6 GHz fractional-N PLL utilizing high-order digital modulation and weighted 13-tap finite impulse response (FIR) filtering for low spur and enhanced noise reduction is implemented in 65 nm CMOS. The prototype PLL exhibits nearly -100 dBc/Hz in-band noise contribution and -126.8 dBc/Hz phase noise at a 3 MHz offset from a 1.8 GHz carrier. With 5th-order single-loop ΔΣ modulation, the fractional...
This paper describes a method to control the zeroes in the frequency response of hybrid finite impulse response (FIR) filter in SigmaDelta fractional-N PLL for quantization noise reduction. By adjusting the current allocation in different branches of the charge pump, transfer function of the FIR filter can be customized to meet various system requirements. Simulation results shows that the proposed...
This paper describes a noise filtering method for ???? fractional- N PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the ???? modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach...
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