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This paper describes a dual-path phase locked loop (PLL) design which automatically tunes to capture the desired frequency as well as the input control voltage range of the dual-path LC voltage-controlled oscillator (VCO). A hybrid automatic frequency calibration (AFC) circuit provides digital frequency calibration and mixed-mode continuous frequency tuning. Since the hybrid AFC circuit independently...
This paper proposes a reconfigurable automatic frequency calibration (AFC) module for software-defined radio (SDR) application which is designed for 200MHz~6GHz communication standards. A 6-bit capacitor array controls VCO output frequency from 3.05-6.12GHz. A fast locking technique featuring code estimation and binary search algorithm is proposed and verified by transistor-level simulation in 0.13μm...
This paper describes a noise filtering method for ???? fractional- N PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the ???? modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach...
A 2 GHz differentially tuned CMOS monolithic LC-VCO was designed and fabricated in 0.18-mum CMOS process. The VCO has a 16.15% tuning range (from 1.8998 GHz to 2.2335 GHz) due to a combination of analog and digital tuning technique (4-bit binary switch-capacitor array). The measured phase noise is -118.17 dBc/Hz at 1 MHz offset from 2.158 GHz carrier. With the presented smart switch, the phase noise...
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