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This paper explores a new design approach of a low-power high slew rate CMOS voltage buffer. The buffer is based on the Flipped Voltage Follower Pseudo Differential Pair, but the bulk-driven technique is utilized at the input stage to achieve rail-to-rail operation. This buffer has been designed for a 0.35μm CMOS technology to operate at a 1.8V supply voltage. The BSIM3 simulated results are provided...
A power-efficient rail-to-rail CMOS analogue voltage buffer is presented. It consists of a complementary pair of super source followers, but a bulk-driven input device with the replica-biased scheme is utilised to eliminate the DC level shift, quasi-floating gate transistors to achieve class-AB performance, and a current switch which shifts between the complementary pair to allow rail-to-rail operation...
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