The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We describe a multiple reference and multiple block size motion estimation (ME) hardware design for professional encoder LSIs, that supports H.264/AVC high 4:2:2 profile, MPEG-2 4:2:2 profile and MPEG-4. An 8times8-based "telescopic" integer motion estimation (IME) followed by an "inclusive" variable block size fractional motion estimation (FME) results in a performance almost...
Increasing level of process variation in the sub-100 nm silicon technology is becoming an important issue. In this paper we describe an approach to estimate the impact of process variations on the static CMOS and the dual-rail PLA down to 32 nm process. This approach is built on accurate variation modeling, published data including the ITRS, Predictive Technology Models, and Monte-Carlo analysis....
This paper presents an exact method which finds the minimum factored form of an incompletely specified Boolean function. The problem is formulated as a quantified Boolean formula (QBF) and is solved by general-purpose QBF solver. We also propose a novel graph structure, called an X-B (exchanger binary) tree, which implicitly enumerates binary trees. Using this graph structure, the factoring problem...
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard cells and the proposed method automatically creates yield-enhanced cell layouts by de-compacting the original cell layout. However, the careless modification of the original layout may degrade its performances severely. Therefore,...
This paper presents a new dual-rail PLA with 2-input logic cells. The 2-input logic cells composed of pass-transistors can realize any 2-input Boolean function and are embedded in a dual-rail PLA without degradation of circuit performance. By using the logic cells, some classes of logic function can be implemented in a smaller circuit area, so that a high-speed and low-power operation is also achieved...
We have developed a circuit design which uses heterogeneous pipelines and latches to maximize hidable clock skew and jitter. With it, the hidable portion of the sum of clock skew and jitter is as large as a fourth of cycle time. In 0.15-µm CMOS LSIs of 500-MHz and 1- GHz based on our new design, performance was, respectively, 22% and 66% better than that of similar FF-based LSIs. We have also developed...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.