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Thin film devices (FDSOI) are among the most promising candidates for next device generations due to their better immunity to short channel effects (SCE). In addition, the introduction of high-k and metal gate has greatly improved the MOSFETs performance by reducing the electrical oxide thickness (CET) and gate leakage current. However, if midgap metal gate is sufficient to provide a high symmetrical...
For the first time, we demonstrate low-VT (VTlin ±0.32V) nMOS and pMOS adjusted in a gate first FDSOI technology by work-function engineering of TiN/TaAlN metal gates. Especially, for low-VT pMOS, various Chemical-Vapor-Deposited TaAlN stacks with optimized Al concentration have been studied to finely tune the work-function above midgap while maintaining good reliability and mobility. Short channel...
We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local and intrinsic VT-variability performances are obtained (AVT=1.45mV.μm). This leads to 6T-SRAM cells with good characteristics down to VDD=0.5V supply voltage and with excellent Static Noise Margin (SNM) dispersion across the wafer (σSNM<;SNM/6) down to VDD=0.7V. We...
In this paper it is shown that HfO2 and HfZrO oxides suffer from large VT instabilities, up to 230mV, when the device width (W) is scaled down to 80nm. It is explained by undesirable lateral oxygen diffusion through the spacers, which mainly modifies the metal workfunction in narrow transistors. HfSiO(N) oxides exhibit a much better immunity to this effect, attributed to a different crystallinity...
We combine a LArge Tilt Implanted-Sloped Trench Lsolation(LATI-STI) for NMOS and Diffusion Doped Trench Sidewalls for PMOS devices to achieve 0.70??m pitch isolation. High performance periphery devices and high endurance Flash Memories cells of the 64Mbit generation and beyond are obtained. The trench refill oxide thickness uniformity and dishing after Chemical Mechanical Polishing(CMP) are optimized...
This paper will describe the characterization and electrical optimization of a high performance Atomic Layer Engineered Sealed Interface Local Oxidation (ALESILO) field isolation process steps. This process uses a vacuum load-lock equipped cluster vertical furnace (fig. 1). That allows perfectly controlled nitride/silicon interface sealing avoiding any extra RTN step[1] to achieve 100 nm range bird's...
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