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This paper addresses the stability problem for switched systems with time-varying delay and parametric uncertainties. The main idea is to construct new piecewise time-varying Lyapunov functionals/functions such that they are decreasing at switching time instants in spite of their discontinuity at those switching time instants. Then the constructed piecewise time-varying Lyapunov functionals/functions...
An 800 MHz digital PLL with its TDC embedded within the DVCO is implemented in 65 nm CMOS and occupies 0.027 mm2. The design requires no calibration and achieves the fractional-N operation without a multi-modulus feedback divider. To further improve the TDC linearity, mismatch filtering is used to achieve a DNL of less than 3.5% of LSB.
This paper presents dimensioning of an IP-based UMTS Terrestrial Radio Access Network (UTRAN) with multiple Node Bs connected to one RNC, where the applied QoS architecture is based on Differentiated Service (DiffServ) with an integrated Weighted Fair Queue (WFQ) and Strict Priority (SP) scheduling. To provide an appropriate network dimensioning for guaranteeing a desired end-to-end QoS, a general...
We investigated the system performance of variable slowlight buffers based on cascaded silica micro-resonator-rings. Continuous tunable buffering to wavelengths of choice is achieved, without losing any packets in an optical packet switching network.
Dynamic reconfiguration for fine-grained architectures is still associated with significant reconfiguration costs. In this paper, a new placement algorithm is proposed to reduce the size of FPGA reconfiguration bitstream. The algorithm is modified on the existing placement algorithm within VPR. It introduces the CLBs configuration of the previous circuit into cost function to increase similarity of...
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