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In this paper, the effect of negative bias temperature instability (NBTI) on MBUs sensitivity of 65 nm bulk technology memories is analyzed and simulated by Geant4. A MTTF reliability model including NBTI stress time is proposed for memories protected by error correction codes (ECCs). Both cases of scrubbing and nonscrubbing are considered. By using the proposed model, the predicted MTTF results align...
In this paper, a novel low-power and highly reliable radiation hardened memory cell (RHM-12T) using 12 transistors is proposed to provide enough immunity against single event upset in TSMC 65 nm CMOS technology. The obtained results show that the proposed cell can not only tolerate upset at its any sensitive node regardless of upset polarity and strength, but also recover from multiple-node upset...
Soft errors, a concern for space applications in the past, became a critical issue in deep sub-micron VLSI design for the continuous technology scaling. An automated fault injection technique is employed to characterise the recovery coverage and soft error sensitivity of the VHDL based design. Lexical and syntax analysis technique is developed to perform automated fault injection task. Stratified...
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