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An 8 Gb/s/link power optimized controller memory interface is implemented in TSMC 40 nm G CMOS process. It is composed of 32 differential data links to support 32 GB/s payload. The bimodal drivers of the request bus enable support of both 12 bits of 2 Gb/s/link single-ended RSL (rambus signaling level) for existing XDRTM memory and 6 bits of 8 Gb/s/link differential signaling for next generation XDR2...
SOI technology is well suited for high speed digital circuits. However, its history effect due to the floating body poses a major challenge to analog circuits. This paper presents the design of a high-performance IO interface (FlexIOtrade) used in Cell Broadband Enginetrade processors , currently in mass production. The design has been scaled across 90 nm, 65 nm, and 45 nm SOI CMOS processes. The...
A transceiver for a memory controller operating at 16 Gb/s per link is implemented in 65 nm CMOS process. Timing calibration, equalization and diagnostic circuits for both memory read and write are on the controller to optimize the overall system performance and cost. A 5-tap TX FIR and a continuous time RX equalizer with active inductor loads are employed. The transceiver also includes a diagnostic...
An asymmetric memory interface cell with 32 bidirectional data and four unidirectional request links operating at 16 Gb/s per link is implemented in TSMC 65 nm CMOS process technology. Timing adjustment and equalization circuits for both memory read and write are on the controller to reduce the memory cost. Each link operates at a maximum rate of 16 Gb/s with sufficient and comparable margins in both...
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