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This paper presents an enhanced path delay fault simulator for combinational circuits. The main objective of this work is to improve the simulation time of path delay fault testing. Our experiments consider K-longest path sets of ISCAS'85 benchmark circuits, and 10M single input change (SIC) test patterns were applied and repeated ten times in order to cover statistical variations. The experimental...
Delay faults in content addressable memories (CAMs) is a major concern in many applications such as network routers, IP filters, longest prefix matching (LPM) search engines and cache tags where high speed data search is significant. It creates the need for analysis of critical paths and detecting associated faults using minimum number of test patterns. This paper proposes a test method to detect...
Delay faults in content addressable memories (CAMs) is a major concern in many applications such as network routers, IP filters, longest prefix matching (LPM) search engines and cache tags where high speed data search is significant. It creates the need for analysis of critical paths and detecting associated faults using a minimum number of test patterns. This paper proposes a test method to detect...
This paper presents SIC based test stimuli with Arithmetic Built in Self-Test (ABIST) concept in order to detect the path delay faults. The presented generator with ABIST stimuli is quite useful for detecting the K-longest path-delay faults of the microprocessor. This paper extends the work of Ø. Gjermundnes and presents its application and validation to the Intel 8051 microprocessor. The experimental...
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