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Gain-cell embedded DRAM (GC-eDRAM) is an interesting alternative to SRAM for reasons such as high density, low bitcell leakage, logic compatibility, and suitability for 2-port memories. The major drawbacks of GC-eDRAMs are their limited data retention times (RTs) and the large spread of RT across an array, which degrade energy-efficiency due to refresh cycles. While the array refresh rate can be determined...
Continuous technology scaling has made traditional Static Noise Margin metrics for stability analysis of SRAM bitcells insufficient. Today, Dynamic Noise Margin analyses and metrics are necessary for state-of-the-art bitcell design, especially under problematic low-voltage operation. In this paper, we overview the concept of state-space modeling for dynamic stability analysis, and then develop an...
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