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The conventional dummy fill insertion operation is usually conducted by foundries without taking into account circuit performance. In this paper, we propose a graph-based scheme to first modify layout interconnect geometry to improve pattern density uniformity in the analog layouts before the traditional dummy fill insertion process as an optional stage. The original analog constraints can be still...
In this paper, we propose a rule-based OPC (RB-OPC) algorithm considering process variation (PV) and integrate it into an analog layout retargeting platform. We apply interconnect wire operations during the retargeting process to compensate the accuracy limitation of the RB-OPC method. A PV-band shifting scheme is used to handle PV-induced-mismatch on circuit matching blocks. From our experimental...
Parasitic capacitance of interconnects in the analog and mixed-signal VLSI circuits can be modeled by using physics equations or empirical curve fitting. In this paper, we propose an analytical model for computing parasitic capacitance between interconnects on different layers or on the same layer. In our method, electric flux is approximated to model different capacitive components, which combine...
In this paper a fast parasitic-aware synthesis approach of CMOS analog circuit is presented. Instead of the conventional approach of circuit sizing followed by layout generation, extraction and verification, we propose a method that considers the performance constraints and layout induced parasitics simultaneously within a concurrent phase of circuit synthesis. The proposed methodology is tested with...
Layout parasitics can significantly affect the performance of analog integrated circuits (ICs). In this paper, a systematic method of optimizing an existing analog layout considering parasitics is presented for technology migration and performance retargeting. This method represents the locations of layout rectangle edges as variables and extracts circuit and layout integrity such as device symmetry,...
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