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As an indispensable portion in the modern system-on-chip designs, analog circuits are becoming more intractable and error prone in the time-consuming design process due to the nature of high parasitic sensitivity along with the shrinking design window in the advanced technology. Compared to the digital counterpart, analog circuits need to be designed more carefully taking into account special analog...
In this paper a fast parasitic-aware synthesis approach of CMOS analog circuit is presented. Instead of the conventional approach of circuit sizing followed by layout generation, extraction and verification, we propose a method that considers the performance constraints and layout induced parasitics simultaneously within a concurrent phase of circuit synthesis. The proposed methodology is tested with...
This paper presents a solution to handling complex multi-group symmetry constraints in the placement design using transitive closure graph (TCG) representation for analog layouts. We propose a set of symmetric-feasible conditions, which can automatically satisfy symmetry requirements. We also develop a new contour-based packing scheme with time complexity of O(g??n??lgn), where g is the number of...
Performance of analog circuits is highly sensitive to layout parasitics. This paper presents an improved algorithm that automatically conducts performance-constrained parasitic-aware retargeting and optimization of analog layouts. In order to meet the desired circuit specification, performance sensitivities with respect to layout parasitics are first determined. Then the algorithm applies sensitivity-based...
VLSI analog module placement problem is NP-complete, and both simulated Cauchy annealing and simulated Boltzmann annealing approaches are widely employed as the search engine nowadays. These approaches, however, exhibit low execution efficiency and pose high degree of difficulty in tuning. In this paper, we present a very fast simulated re-annealing placement algorithm for analog VLSI layout design...
In this paper, a layout synthesis tool for the design of analog integrated circuits (ICs) is presented. This tool offers great flexibility that allows analog circuit designers to bring their special design knowledge and experiences into the synthesis process to create high-quality analog circuit layouts. Different from conventional layout systems that are limited to the optimization of single devices,...
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