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A 64-b RISC (reduced-instruction-set-computer) microprocessor that performs a load/store instruction in one clock and achieves 40 MIPS and 20-MFLOPS peak performance at 40 MHz clock is described. Two techniques are used to attain this performance: (1) two translation lookaside buffers (TLBs) with parallel and hierarchical word-line transition detection circuits; (2) a self-clocked register file using...
In the CMOS cross-point LSI described, fully synchronous switching capability for fixed-length ATM cells (packets), as well as the functions of conventional cross-point switches, has been realized. Packet broadcast capability has also been achieved as the result of input-oriented bit-map routing architecture. In order to exchange 32 packet links at the broadband line speed, tristate buffers and control...
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