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Pipelined ADCs designed in analog BiCMOS technologies can offer good linearity and high SNR performance for input signals with reasonable voltage swings. Such ADCs, however, face two critical design challenges: the process limits the sampling rate, and the pipeline architecture limits power efficiency. This paper introduces a two-way time-interleaved (TI) switched-current 1Gs/s 12b pipelined ADC in...
A 16b 160MS/S pipelined ADC built in a complementary SiGe BiCMOS process is presented, with an SFDR of 105dB and an SNR of 77dB at -1dBFS below 160MHz. The fully buffered track-and-hold has circuitry needed to achieve this performance. The internal sub-DAC uses circuits to mitigate the limitations imposed by transistor self-heating, early voltage and impact ionization.
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