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A test structure for reliability analysis of MOSFETs in CMOS inverters under DC and high frequency AC stress has been presented. It has an input pulse generation block with a ring oscillator, monitor inverter blocks and Kelvin connected selector switches. Detailed I – V characteristics of MOSFETs in the monitor inverters were measured and the degradation by HCI and BTI in nMOS and pMOS devices were...
Orientation dependence and asymmetry of VT (threshold voltage), gm (transconductance), S (subthreshold slope), and Ioff (off-state current at VG =3D 0 V) in 0.18 ??m n-MOSFETs were measured and analyzed. The test structure contains 8 different channel orientation angles of 0??/45??/90?? and three kinds of process conditions. Although VT, gm and S scarcely show particular anisotropy except for the...
Information on false paths is useful for design and test. Since identification of false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, the correspondence has been established only by some restricted...
A test structure with a wide channel width for analysis of hot-carrier-induced photoemission is presented and spectrum changes for 90 nm MOSFETs under DC (direct current) and AC (alternating current) operation are discussed. Comparing with DC operation, photon counts for higher photon energy increase under AC operation, and spectrum curves change with rise and fall time of gate pulse. The overshoots...
A channel length engineering technique for optimization of primitive cells in standard cell libraries is proposed and a test structure to analyze the operation performance and leakage current of 3-input NAND is presented. Since the topmost transistor (Nl) in the three series connected n-MOSFETs of 3-input NAND has the largest VDS, subthreshold leakage current can be reduced by optimizing a channel...
This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce the notation to analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) the combinationallytestable class and 2) the acyclicallytestable class. Then, we introduce a new class of linear-depthtime-bounded circuits as one of the...
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