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CMOS memories occupy a significant percentage of the Integrated Circuits footprint. With the development of new manufacturing technologies to a smaller scale, performance and reliability challenges exist, namely caused by parametric variations such as Process variations (P), power supply Voltage (V) and Temperature (T), and Aging (A) or, in a general perspective, PVTA variations. The purpose of this...
This paper presents the Scout Flip-Flop, a new performance Sensor for toleranCe and predictive detectiOn of delay-faUlTs in synchronous digital circuits. The sensor is based on a new master-slave Flip-Flop (FF), the Scout FF, with built-in functionality to locally (inside the FF) create two distinct guard-band windows: (1) a tolerance window, to increase tolerance to late transitions, making the Scout's...
The purpose of this paper is to present a new method and structure for the automatic configuration of a digital system to unknown delays in synchronous input data channels. The method makes possible to restore synchronism in node-to-node communication. Synchronism may be lost due to different delays introduced by the various communication channels. The proposed method allows differences in the channel...
The purpose of this paper is to present a novel built-in Clock Domain Crossing (CDC) test and diagnosis methodology for Globally Asynchronous, Locally Synchronous (GALS) systems. The methodology allows design and prototype validation, low maintenance and repair costs, and production / lifetime at-speed test. Moreover, high resolution diagnosis is obtained, to identify which device(s) and/or communication...
In nanometer technologies, as variability is becoming one of the leading causes for chip failures, signal integrity is a key issue for high-performance digital System-on-Chip (SoC) products. In this paper, analysis is focused on the occurrence of Delay-faults due to Power-supply disturbances in nanometer technologies. Using a previously proposed VT (power supply Voltage and Temperature)-aware time...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
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