The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents experimental results on metal oxide semiconductor field-effect transistors (MOSFETs) featuring an array of 1000 trigated uniaxially strained nanowires with a cross-sections of 15 × 15 nm2 in combination with a HfO2/TiN gate stack. The high uniaxial strain along the wires reduces the band gap energy by approximately 140 meV and enhances the electron mobility. Ideal inverse subthreshold...
The chemical reactions at the higher-k LaLuO3/Ti1NX/poly-Si gate stack interfaces are studied after high temperature treatment. A Ti-rich TiN metal layer degrades the gate stack performance after high temperature annealing. The gate stack containing TiN/LaLuO3 with a near stoichiometric TiN layer is stable during 1000 °C, 5s anneals. Both electrical and structural characterization methods are employed...
The integration of lanthanum lutetium oxide (LaLuO3) with a n value of 30 is, for the first time, demonstrated on strained and unstrained SOI n/p-MOSFETs as a gate dielectric with a full replacement gate process. The LaLuO3/Si interface showed a very thin silicate/SiO2 interlayer with a Dit level of 4.5 × 1011 (eV · cm2)-1. Fully depleted n/p-MOSFETs with LaLuO3/TiN gate stacks indicated very good...
Integration of lanthanum lutetium oxide (LaLuO3) with a κ value of 30 is demonstrated on high mobility biaxially tensile strained Si (sSi) and compressively strained SiGe for fully depleted n/p-MOSFETs as a gate dielectric. N-MOSFETs on sSi fabricated with a full replacement gate process indicated very good electrical performance with steep subthreshold slopes of ~72 mV/dec and Ion/Ioff ratios up...
The implementation of more powerful materials into leading edge CMOS devices allows performance improvements without scaling and without changing the circuit design libraries. This highly motivates the research on novel materials. In this paper we present various transistor fabrication processes like “gate first” and “replacement gate” for different channel stack configurations like strained Si, strained...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.