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This paper describes a continuous time DeltaSigma modulator with 10MHz of bandwidth that achieves a DR of 87dB and an IMD of -91dBc while consuming 100mW.
We investigated the dynamic nature of a highspeed CMOS comparator, and present a comparator frequency-response model based on small-signal linear analysis of a latch. The analytical frequency model offers good insight into the linearity of the quantizer utilized in CTDeltaSigma modulators. In addition, a novel design guideline for a high-speed CMOS comparator to ensure the quantizer linearity is presented.
A CT quadrature bandpass ADC is designed for a multi-standard television receiver. When clocked at 264MHz, the ADC achieves 90dB of total DR over an 8.5MHz BW centered at 44MHz. The 4th-order 4b ADC uses a modified feedforward topology and includes 12dB of AGC. The 2.5mm2 chip consumes 375mW in a 0.18mum CMOS process
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