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The paper proposes high speed FPGA implementations of adders and multipliers in Fp. The work shows through experimental results that due to optimized addition chain available in such devices, Karatsuba decomposition upto a particular level improves the performance. Further the paper modifies existing interleaved multiplier using Montgomery ladder and the high speed adder circuits. Extensive experiments...
In this paper, a novel VLSI architecture for one dimensional Walsh-Hadamard transform (WHT) is proposed. The core of the architecture is the HVMA (Hadamard Vector Merging Adder) that adds the products of input data words and transform (Hadamard) matrix elements in parallel using a (4:2) compressor based carry-save tree structure. The core also exploits the Hadamard matrix's property of equal distribution...
The FPGA compilation process (synthesis, map, placement, routing) is a time-consuming process that limits designer productivity. Compilation time can be reduced by using pre-compiled circuit blocks (hard macros). Hard macros consist of previously synthesized, mapped, placed and routed circuitry that can be relatively placed with short tool runtimes and that make it possible to reuse previous computational...
In recent time watermarking technique becomes a potential solution for copyright protection, authentication and integrity verification of digital media. Among the widely used watermarking techniques, spread spectrum modulation based method becomes appealing due to its inherent advantage of greater robustness and is used widely for various applications. Some watermarking applications, for example,...
This paper presents an FPGA based hardware design for full search block matching (FSBM) based motion estimation (ME) in video compression. The significantly higher resolution of HDTV based applications is achieved by using FSBM based ME. The proposed architecture uses a modification of the sum-of-absolute-differences (SAD) computation in FSBM such that the total number of additions/subtraction operations...
This paper presents the architecture and FPGA implementation of a robust GF(p) parallel arithmetic unit. The most efficient modular multiplication, inversion and division units greatly reduce the clock cycles requirement for point operations applicable to elliptic curve cryptography. The parallel arithmetic unit helps to achieve a high speed up in cryptographic applications. The architecture can resist...
This paper presents a reconfigurable architecture of the advanced encryption standard (AES-Rijndael) cryptosystem. The suggested reconfigurable architecture is capable of handling all possible combinations of standard bit lengths (128,192,256) of data and key. The fully rolled inner-pipelined architecture ensures lesser hardware complexity. The work develops a FSMD model based controller which is...
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