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Yields for digital very-large-scale-integration chips have been declining in the recent years, and the decline is accelerating as the technology moves deep into nanoscale. Recently, we have proposed the notion of error tolerance to improve yields for a wide range of high-performance digital applications, including audio, speech, video, graphics, visualization, games, and wireless communication. Error...
Capacitive crosstalk can slowdown transitions which can propagate to outputs and cause erroneous operation. Test generation methods such as XGEN and XGEN-E were proposed to generate tests for such failures. However, a drawback of these test generation methods is that a large proportion of faults are aborted. In this paper, we systematically derive a multi-valued algebra. We first show that a composite...
Sticky path-delay faults are path delay faults that are neither robustly nor non-robustly testable, but cannot be proven functionally unsensitizable. Better characterization of delay test quality requires a proper analysis of sticky path-delay faults. Furthermore, careful elimination of sticky path-delay faults contributes significantly to test development productivity and reduction of delay test...
A new concept called intelligible testing has been recently proposed to improve yields for a class of error tolerant systems, including audio, speech, graphics, video, and digital communications. Error rate, defined as the percentage of clock cycles for which the value at a circuit's outputs deviates from the corresponding error-free value, has been identified as a key measure of error severity. In...
Test generation methodology previously developed for crosstalk targets in the presence of manufacturing defects and process variations results in low coverage. In this paper, under a realistic assumption about the nature of manufacturing defects, we show that by incorporating two new concepts, namely, non- criticality and delay-superiority, significantly higher coverage of targets and lower test generation...
Different tests for a single gate delay fault can detect different ranges of delay fault sizes. It is of interests to determine whether, for most faults, a single test covers all the ranges of delay fault sizes covered collectively by all tests for the fault. Using an enhanced gate delay fault simulation algorithm, we show that for a considerable number of gate delay faults in benchmark circuits,...
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