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Size and complexity of contemporary High Performance Computing (HPC) systems increases permanently. While the reliability of a single component and compute node is high, the huge amount of components comprising these systems results in the fact that defects happen regularly. This drives the need to manage failure situations. Common issues are component failures or node soft lock-ups that typically...
This paper describes a software-based technique for building heterogeneous fault tolerant multi-core systems, which are able to handle temporary and permanent hardware faults autonomously in two system layers. The fault tolerance technique relies on a single concept for adapting the binary code of the user application to the current fault state of a single core. Thereby this scheme is used either...
The available memory bandwidth of existing high performance computing platforms turns out as being more and more the limitation to various applications. Therefore, modern microarchitectures integrate the memory controller on the processor chip, which leads to a non-uniform memory access behavior of such systems. This access behavior in turn entails major challenges in the development of shared memory...
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