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Manufacturing of 3D stacked IC chips has became feasible recently. But testing of these 3D ICs is becoming important in the semiconductor industry. Now a days also embedded core based 3D ICs are equally popular. Hence the increased complexity in the chips becomes a constraint for the test engineers. This paper addresses a 1500-style wrapper optimization in 3D ICs based on Through Silicon Vias(TSVs)...
Manufacturing and operation-induced variations have emerged as a critical challenge in designing integrated circuits (ICs) under the nanometer technology regime. Most work on addressing variations has focused on device, circuit, and logic-level solutions. As the magnitude of parameter variations increases with technology scaling, these techniques are not sufficient to address the negative impact that...
In the fast paced world of IC design, companies strive for ways to create competitive, robust designs, while delivering speedy time-to-market results. A top-down design flow provides a fast, results oriented design methodology, but, at most Universities, the strong legacy of the Mead/Conway approach has lead to custom methods being the default way to teach students VLSI design. This paper discusses...
Increasing power density causes die overheating due to limited cooling capacity of the package. Conventional thermal management techniques e.g. logic shutdown, clock gating, frequency scaling, simultaneous voltage-frequency tuning etc. increase the design complexity and/or degrade the performance significantly. In this paper, the authors propose a novel design technique, which makes a circuit amenable...
Design considerations for robustness with respect to variations and low power operations typically impose contradictory design requirements. Low power design techniques such as voltage scaling, dual-Vth etc. can have a large negative impact on parametric yield. In this paper, we propose a novel paradigm for low-power variation-tolerant circuit design, which allows aggressive voltage scaling. The principal...
Inter-die and intra-die variation in process parameters increases parametric failures and leakage spread in nano-scale memories, leading to significant yield degradation. Design level optimization methods are not sufficient to address the leakage and parametric failures, particularly, under large variation. In this paper, we propose two post-silicon tuning techniques which can simultaneously reduce...
This paper presents HotSpot-a modeling methodology for developing compact thermal models based on the popular stacked-layer packaging scheme in modern very large-scale integration systems. In addition to modeling silicon and packaging layers, HotSpot includes a high-level on-chip interconnect self-heating power and thermal model such that the thermal impacts on interconnects can also be considered...
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