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This paper presents 64-quadrature amplitude modulation (QAM) 60-GHz CMOS transceivers with four-channel bonding capability, which can be categorized into a one-stream transceiver and a two-stream frequency-interleaved (FI) transceiver. The transceivers are both fabricated in a standard 65-nm CMOS technology. For the proposed one-stream transceiver, the TX-to-RX error vector magnitude (EVM) is less...
A low-power and small-area 60-GHz CMOS transmitter with oscillator pulling mitigation is presented. The subharmonic injection locking technique for the suppression of pulling effects is analyzed and demonstrated. The transmitter fabricated in a 65nm CMOS process achieves 7.04-Gb/s data rate with an EVM performance of −25 dB in 16QAM. The whole transmitter consumes 210 mW from a 1.2-V supply and occupies...
Helium-3 ion irradiation technique is proposed to improve silicon substrate noise isolation by creating a local semi-insulated region with a resistivity over 1kΩ-cm in low-resistive silicon substrate. Noise isolation is improved about 10dB at 2GHz after helium-3 ion irradiation in a 180-nm CMOS process. A 90% noise reduction has been achieved in the measurement results for test structures with guard...
An area-efficient 60-GHz wake-up receiver (WuRx) using reconfiguration techniques of multistage low-noise amplifiers (LNAs) is presented. The gain stages of the 60-GHz LNA are reused as the envelope detectors for the wake-up receiver. Therefore, the bulky components such as extra switches between the wake-up receiver and the LNA, additional antennas, and excess input matching network can be removed...
A 60-GHz CMOS on-chip dipole antenna with efficiency-enhancement technique is presented. A helium-3 ion irradiation process is used to reduce the substrate losses of the on-chip antenna. The radiation efficiency of the antenna is doubled using the ion implantation technique. The antenna is fabricated in a 65-nm CMOS technology with a core area of 0.48 mm2. The on-chip antenna achieves a peak gain...
A 60-GHz CMOS transmitter with on-chip antenna for high-speed short-range wireless interconnection is presented. The radiation efficiency of the on-chip antenna is doubled using substrate loss improvement techniques. The transmitter fabricated in a 65-nm CMOS process achieves over 5Gb/s data rate with an EVM performance of −12 dB for BPSK modulation. The whole transmitter consumes 17 mW from a 1.2-V...
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