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A 3.4 Mb SRAM macro is developed with a built-in stability sensor for adaptive wordline under-drive (AWLUD) in 32 nm HK-MG CMOS technology. By tracking temperature, voltage and process variation of each die, the AWLUD is shown to lower VCCmin by 130 mV, increase yield by 9% at a target frequency, and is projected to reduce test time up to 40% by eliminating die-by-die WLUD programming.
CMOS technology has followed Moore's law into the nanoscale regime where SRAM scaling is facing increasing challenges in gaining performance at reduced leakage power for future product applications. Despite the advances in process technologies and the resultant ability to produce ever-smaller feature sizes, the increasing variations of scaled devices in SRAM are playing an increasingly important role...
A high-performance low-power 153 Mb SRAM is developed in 45 nm high-k Metal Gate technology. Dynamic SRAM PMOS forward-body-bias (FBB) and Active-Controlled SRAM VCC in Sleep are integrated in the design to lower Active-VCCmin and Standby Leakage, respectively. FBB improves the Active-VCCmin by up to 75 mV, and Active-Controlled SRAM VCC distribution tightened by 100 mV, both of which result in further...
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