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Structured ASIC has been introduced to bridge the power, performance, area and design cost gaps between ASIC and FPGA. As technology scales, leakage power consumption becomes a serious problem. Among the leakage power reduction techniques, power gating is commonly used to disconnect idle logic blocks from power network to curtail sub-threshold leakage. In this paper, we apply power gating to structured...
This article studies a new circuit acyclic clustering problem which divides a combinational circuit into groups of sub-circuits, each of which has limited numbers of inputs and outputs. Several heuristics are proposed to solving this problem. We achieve 300% speedup on logic simulation, with an application of our approach, for finding an input vector that incurs minimum or maximum leakage power dissipation.
A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-configurable logic block (VCLB). We design a 0.18 um standard cell library based on our VCLB and establish a design flow using as many commercial tools as possible. We also propose a method to evaluate the viability of a...
Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited capability of placing more double vias (called vial) between metal 1 and metal 2. Such a limitation is caused by the way we design the standard cells and can not be resolved by developing better tools. This paper presents a...
On-chip bus encoding was previously shown not viable for energy reduction based on same wire-pitch assumption. In this paper, we revisit this issue not only from the energy but also from the delay and codec overhead perspectives. With the same routing area for each encoding method, we show that all investigated methods including those using more redundant wires for crosstalk avoidance are not viable...
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