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Crosstalk is an increasingly significant effect for VLSI timing performance. Traditional STA or SSTA techniques provide pessimistic crosstalk analysis based on timing window envelopes. In this paper, we present input-aware signal probability-based statistical timing analysis (SPSTA) taking crosstalk-induced delay variations into account. SPSTA achieves reduced pessimism and improved accuracy by signal...
Nanoscale VLSI systems are subject to an ever increasing performance variability, which hinders performance scaling and increases verification complexity. In this paper, we study an often neglected source of performance variability, namely logic inputs or system workload. We present input-aware statistical timing analysis, which gives not only critical path delays but also critical path activating...
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