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The tunneling field effect transistor (TFET) is a device concept that has the potential to outperform CMOS technology both in energy efficiency and speed. One of the challenges for this device concept is to improve on-currents to meet industry standards. In order to attain this goal, a number of modifications to the basic design, concerning both material as well as geometry variations, have been proposed...
Addressing applications such as high performance RF power amplifiers and DC/DC converters with high conversion efficiency we demonstrate a cost effective integration of a complementary medium voltage RF LDMOS module in a 0.25 μm base CMOS flow. The integration of the NLDMOS and PLDMOS transistors requires just three additional mask steps. The NLDMOS has an excellent large signal RF performance...
In this paper we present different large-scale heterogeneous integration technologies for optical MEMS that enable the integration of optical MEMS with standard CMOS-based ICs. Examples that are presented include various mono-crystalline silicon micro-mirror arrays and infrared bolometer arrays.
The integration of RF NLDMOS transistors into a 0.13 μm CMOS process for operating at X-Band (8.5-10.5 GHz) frequencies with over 11 dB gain and 0.25 W/mm power density and 22% power added efficiency at 1 dB output power compression is presented. The self aligned NLDMOS was modularly integrated into IHP's 130 nm SiGeC BiCMOS platform targeting 1 W X-Band power amplifiers for radar and satellite communication...
The front-end electronics (signal amplification and summation) of the ATLAS Hadronic End-cap Calorimeter (HEC) is operated at the circumference of the HEC calorimeter wheels inside the cryostats in liquid argon (LAr). The present electronics is designed to operate at irradiation levels expected for the LHC. For operation at the sLHC the irradiation levels are expected to be a factor ten higher, therefore...
This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676mum2 and 0.54mum 2 SRAM cells, optimized for performance and density, respectively. The key focus of this technology has been low cost, process simplicity and...
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