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Wirelength is a traditional optimization objective in global placement algorithms. To eliminate cell overlaps, spreading forces need to be added to pull cells away from highly congested areas. At the same time, to optimize wirelength, the quadratic nature should be maintained. In this paper, several techniques are proposed to optimize spreading force orientation and modulation. Specifically, a percentage-driven...
Clock networks dissipate a significant fraction of the entire chip power budget. In contrast to most of the traditional works that handle the power optimization problem with clock routing or buffer sizing, we propose a novel register clustering methodology for power reduction of clock trees. Moreover, a fast three-stage clock tree synthesis (CTS) approach based on register clustering is presented...
Clock networks dissipate a significant fraction of the entire chip power budget. Therefore, the optimization for power consumption of clock networks has become one of the most important objectives in high performance IC designs. In contrast to most of the traditional works that handle this problem with clock routing or buffer sizing, this paper proposes a novel register clustering algorithm in generating...
In this paper, we propose a fast placer for FPGA placement on a new commercial hierarchical FPGA device. The novelty of this research lies in the application of a multilevel V-shape optimization flow including an architecture related cluster process and a constructive placement. The new placer can handle large-scale FPGA placement problem quickly. Experimental results show that the proposed placer...
In this paper, we present a multilevel hierarchical FPGA (MFPGA) architecture model and propose a cluster-based placement algorithm for this model. The algorithm has a multi-scale optimized V-shape flow including constructive bottom-up clustering process and top-down placement process. Experimental results indicate that our algorithm improves total wire-length and logic utilization by more than 15%...
In this paper we present a multilevel hypergraph partitioning algorithm which satisfies not only vertex weight constraint but also edge weight constraint. In our multilevel paradigm, two FM (Fiduccia and Mattheyses, 1988) variants are performed alternately in the refinement stage. The first FM variant aims to symmetrize edge weight of the two partitioning blocks and the other aims to minimize cut...
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