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Dual-Vth design is an effective leakage power reduction technique at behavioral synthesis level. It allows designers to replace modules on non-critical path with the high-Vth implementation. However, the existing constructive algorithms fail to find the optimal solution due to the complexity of the problem and do not consider the on-chip temperature variation. In this paper, we propose a two-stage...
The technique of cell shifting has the advantage of linearly smoothing the overlap in placement. In the shifting process we should preserve the integrity of the original placement as much as possible and do less damage to the relative locations of the cells. The current cell shifting methods only locally or globally smooth the density without considering the relation between the local and the global...
Leakage power is becoming a key design challenge in current and future CMOS designs. Due to technology scaling, the leakage power is rising so quickly that it largely elevates the die temperature. In this paper, we deeply investigate the impact of leakage power on thermal profile in 2D and 3D floorplanning. Our results show that chip temperature can increase by about 11 V in 2D design and 68 V for...
Increasing buffer number for future technology makes traditional one-pass-flow (timing driven placement is followed by buffer insertion and legalization) failed, since accommodation for buffers significantly disturbs original design. This paper exploits the delicate relationship between buffer insertion and timing driven placement, and proposes a novel method to incorporate buffer insertion during...
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