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For emerging deep-subwavelength lithography technologies (90 nm and following) the data volume and the complexity of optical proximity correction (OPC) have increased dramatically. This has added to the total cost of IC manufacturing and become an increasingly critical issue in optical lithography. In this paper, we present a new method of implementing hierarchical OPC to explore its merits in runtime...
To reduce design spin time, OPC-unfriendly spots in IC layout should be found out by designer before tape-out. This can be done by firstly running a "trial OPC" step on the layout, followed by running an OPC step to verify the result. In this paper we introduce a new OPC algorithm using an edge bias modeling method. When given a piece of sample post-OPC layout, software based on this algorithm...
For emerging deep-subwavelength lithography technologies (65 nm and following) the computation cost and complexities of the conventional resolution enhancement technologies (RET) such as optical proximity correction (OPC) are themselves becoming bottlenecks in the IC manufacturing flow. This has motivated the recent calls for faster and more flexible solutions. In this paper, we present a new algorithm...
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