The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The feasibility of geometric magnetoresistance (MR) measurement from linear to saturation operation regime is demonstrated in ultrathin body and BOX fully depleted silicon-on-insulator devices from 14-nm technology node. Besides, we propose a new physical compact model for MOSFET drain current under high field transport, which reproduces experimental MR mobility from linear to saturation operation...
Since the introduction of silicon nanowire field-effect transistors (SiNW FETs) as a new technology for highly integrated circuits, their scaling behavior has been of crucial importance for the continuation of Moore's law. To date most studies have been of a theoretical nature, as small wire spacing is difficult to achieve experimentally. Here we successfully fabricated and investigated arrays of...
The surface roughness scattering in n-type FinFET devices is accurately analyzed based on mobility measurements at low temperatures. Using the top/side wall current separation technique, the effective mobility for each surface has been extracted. Considering the second order mobility degradation factor, the surface roughness scattering of top and sidewall conduction has been quantitatively compared.
With the process scaling, the leakage current reduction has been the primary design concerns in a nanometer-era VLSI circuit. In this paper, we propose a new lithography process-aware edge effects correction method to reduce the leakage current in the shallow trench isolation (STI). We construct the various test structures to model Ileakage and Ileakage_fringe which represent the leakage currents...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.