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Optimization of halo profile for advanced MOSFET device is known to be very critical and challenging. Halo profiles around channel can cause carrier mobility degradation, leakage and higher Vt mismatch. Indium and high scattering P-type dopant (HS-P) mixed halo formation have been used widely for n-FET devices. Gallium has a better activation than Indium and is heavier specie than HS-P. Gallium could...
This paper studies how boron thermal diffusion in SiGe heterostructure are influenced by different source drain extension high-energy fluorine implant after SiGe thermal process for advanced HKMG SRAM device. Different fluorine profiles may introduce different fluorine concentration along Si/SiGe interface and result in fluorine interstitial cluster at different SiGe positions after SiGe 700°C thermal...
In this paper, we have demonstrated that cryogenic implantation applied to source and drain (SD) extension, pocket/halo and SD formation offers advantages for higher core and SRAM driving current and one order lower Ioff bulk (Ioffb) leakage in NMOS with reduced SRAM defectivity. Atomistic Kinetic Monte Carlo (KMC) modeling confirms that the cryo-implantation has enabled a unique control of active...
In summary, we have designed and fabricated a DBI for mobile DRAM I/O interface in 65nm CMOS to obtain an aggregate data throughput of 8.4Gb/s and 10Gb/s on FR4 and Roger test boards, respectively, with power consumptions of 21 mW and 25mW. The BERs for both test boards are measured as <;1x10-15 by using 223-1 PRBS from the Agilent-70843C.
This paper presents a state-of-the-art 28nm CMOS technology using conventional poly gate and SiON gate dielectric (Poly/SiON) with best-in-the-class transistor performance, SRAM SNM (static noise margin), MOM capacitance density and mismatch, and ULK (k=2.5) interconnect. The ION are 683 and 503 uA/um (at IOFF = 1nA/um, VDD=1V) for the n- and p-MOSFET, respectively. (With normalized tOX and VDD, these...
This paper proposes a design of IT memory cells that utilizes the modulation of drain current by channel traps and offers these advantages: 1. capacitorless structure, 2. long data retention time, 3. excellent endurance characteristics, 4. low power consumption, 5. 3D integration compatibility.
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