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We demonstrate for the first time, Si1−xGex channel trigate PFETs on insulator with aggressively scaled fin width WFIN, gate length LG, and high-K/metal-gate stack (inversion oxide thickness TINV = 1.5 nm) using an implant-free raised source/drain (RSD) process. We report excellent electrostatic control down to LG = 18 nm for WFIN ≤ 18 nm. Using an optimized RSD process, we achieved high-performance...
<para> The dependence of the performance of strained NMOSFETs on channel width was investigated. When the channel width was varied, the stress in the channel varied accordingly. This changed the electron effective mass and, consequently, the <emphasis emphasistype="smcaps">on</emphasis>-state current . By shrinking the channel width of a strained NMOSFET from...
Laser scattering surface maps of polysilicon films are studied under a range of process conditions. The surface maps are shown to contain information that correlates with polysilicon film morphology which impacts device performance within a CMOS process for the 45 nm node. These surface maps provide whole wafer surface information at a data collection throughput of 1 minute per wafer. They provide...
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