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This paper describes a low-power 25-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. The ADC employs a novel low-energy and area-efficient tri-level switching scheme in the DAC. Compared to the conventional SAR ADC, the average switching energy and total capacitance are reduced by 97% and 75%, respectively. Asynchronous design is implemented...
This paper presents a non-binary passive charge sharing SAR ADC and an optimization method for non-binary successive approximation algorithm. The passive charge sharing ADC is designed. The optimization method suggests that the non-binary SAR ADC with lower standard deviation DAC capacitance values will show better static performance. The SAR ADCs with different standard deviation value of DAC capacitor...
This paper presents a novel charge-redistribution successive-approximation register (SAR) analog-to-digital converter (ADC). The proposed ADC is based on a novel capacitive DAC switching scheme which employs unit capacitors for voltage sampling and charge redistribution. Compared with published capacitive DAC which uses the same unit size capacitor, the proposed DAC needs only 33% of the total switches...
This paper presents a novel switching scheme for an ultra-low energy charge-redistribution digital-to-analog converter (DAC) to be used in successive-approximation register (SAR) analog-to-digital converter (ADC). The proposed scheme employs unit capacitors for voltage sampling and charge redistribution. Compared with previously published capacitive DAC which uses the same unit size of capacitor array,...
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