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Scaling of source/drain extension junctions continues to be a major focus for sub 45 nm planar CMOS process development. Device scalability, drive current, and leakage performance are determined by junction depth, activation, and residual disorder. These requirements have driven ion implants into the deep sub-keV regime and integration of millisecond anneals for activation. In this paper, we introduce...
Millisecond annealing is a key enabling technology for creating the ultra-shallow junctions of the 65 nm node and beyond. The very short thermal diffusion distances inherent in millisecond annealing exacerbate larger scale pattern density differences and can result in corresponding differences in annealing temperatures. This paper considers the three different methods of achieving millisecond annealing...
High energy borane (B2H6) gas cluster ion beam (GCIB) successfully enables a sub-10 nm box-shaped dopant profile without channeling tail, and steep gradient (2.5 nm/dec) in lateral direction. pFET using GCIB source/drain extension shows superior suppression of short channel effects and reduces the dependency of drive current on gate overlap capacitance variation for scaled devices. Moreover, the perimeter...
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