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This paper explores the FPGA routing architecture based on a new concept of “general switch box (GSB)” to improve the performance of FPGA. Compared with the existing CB/SB routing architecture and CS-box architecture, the proposed GSB architecture has much larger exploration space. Experimental results with MCNC benchmark circuits show that the performance of FPGAs with GSB is about 24.3% better than...
The cluster-based FPGA can significantly improve timing and routability. Packing is introduced in the CAD flow to pack logic elements into clusters. In order to reduce unnecessary connectivity within a cluster, sparse crossbar FPGA architectures are under investigation. This paper proposes a novel packing algorithm using direct graph searching method and connection gain function. Experimental results...
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