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The rate of aging of ICs is increasing with the continued reduction in feature sizes of devices. Bias temperature instability (BTI) is considered to be the major reliability hazard in nano-scale CMOS and causes stability degradation of SRAM cells. Some of the SRAM cells functioning properly at fabrication may fail during their desired lifetime due to aging. This will cause large aging quality loss...
Negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) cause SRAM stability degradation during its lifetime. Hence, some of the SRAM cells that are functional initially may fail due to aging after usage. This causes field failures of the shipped chips. In this paper we focus on screening out these SRAM cells which may fail after aging during post-fabrication...
Spatial correlation of process variation increases the probability that nearby transistors have similar variation values. However, the impact of spatial correlation on yield enhancement techniques, such as spare rows and columns for SRAM arrays, has not been well understood. In this paper we find that the clustering of failing cells caused by spatially-correlated process variation makes the SRAM array...
Substantial imperfections in carbon nanotube (CNT) field-effect transistors (CNFETs) are one key obstacle to the demonstration of large-scale CNFET circuits. In this paper, we first categorize transistors based on the impact of resizing on yield improvement and delay penalty for logic circuits. Then we propose an approach to size transistors in different categories by using redundant CNTs to improve...
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