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This paper presents a self-testing technique for split-capacitor-array SAR ADC. In the proposed mutual characterization methodology, the capacitor array is reconfigured so that one sub-array assists the bit weight extraction of the other. Taking advantage of the split-capacitor-array architecture, mutual characterization incurs much less area overhead than previous works. From obtained bit weights,...
In this paper, we present, for the 1-bit/stage pipelined ADC, a self-characterization technique that quantifies the per-stage capacitor ratio and comparator offset - the two main nonlinearity sources. In the proposed loop test, two adjacent pipelined stages are reconfigured to form a loop. Then, DC test stimuli are applied. The capacitor ratio and comparator offset of the stage under test are derived...
This paper presents a low-cost wafer-level test methodology for the source driver ICs of liquid crystal displays; the idea is to realize the test circuitry on the wafer scribe line. The proposed technique not only substantially reduces the required ATE I/O channels but also eliminates the need of high-speed digitization units on the ATE. Furthermore, because the test circuitry is realized on the scribe...
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