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This paper proposes a double-end sourced layout for multichip SiC MOSFET power module adopting conventional wire-bonded packaging technology. The unique design provides each MOSFET with two parallel commutation loops by incorporating a symmetrical pair of dc-bus terminals into the power module. This new layout provides symmetrical equivalent power loops to each paralleled MOSFET and thus enables consistent...
A 30kVA SiC MOSFET inverter is developed for 180°C ambient temperature operation. The power structure and gate drivers of the inverter system are designed based on SiC MOSFETs and other high temperature (HT) components. The prototype inverter system has been built, and placed in a thermal chamber of 180°C for testing. The HT operation of the inverter has lasted for more than 85 hours accumulatively...
This paper proposes a wire-bonded design with a unique double-end sourced structure for multi-chip paralleled SiC power modules. The proposed design achieved a reduced power-loop inductance of 7.2 nH, while inheriting the advantages of the conventional wire-bond technology. More importantly, the symmetrical structure of the proposed design brought consistent performances to the paralleled devices...
A 30kVA SiC MOSFET inverter is designed and evaluated for 180°C ambient temperature operation. The entire inverter system is designed for high temperature (HT) except the DSP control circuit in room temperature environment. The power structure is designed using SiC MOSFETs and HT capacitors. The gate driver circuits with protections are also designed for the HT environment. The prototype has been...
This paper proposes an improved wire-bonded design with a unique double-end sourced (DES) structure for multi-chip paralleled silicon carbide (SiC) power modules. The new structure adopts two pairs of DC bus-bars to source the power module from the two ends, not only shortens the equivalent power loops but also provides a symmetrical structure for the paralleled devices. The proposed design achieved...
This paper investigates the impact of gate-loop layouts on the switching loss of a multi-chip silicon carbide metal-oxide-semiconductor field-effect-transistor (MSOFET) power module. Six gate loop layouts are proposed and evaluated in switching simulations. A 16.2% difference on the total switching loss is observed between a good and a bad gate loop layout. The results shows that the total switching...
This paper investigates the power module design for better common-mode (CM) noise performance. A high frequency full-bridge diode rectifier is studied as an example. For this circuit, a comprehensive parametric study and a proposed CM equivalent model are first presented to identify the most influential factors in CM noise generation and mitigation. It is shown that proper parasitic value and parasitics...
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