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The reconfigurable multi-function matrix operation (MFMO) module circuits including eigen-value and eigen-vector decomposition (EVD), QR factorization (QRF), linear system solver (LLS), and matrix multiplier (MM) for the software defined radio and cognitive applications are designed using coordinate rotations digital computer (CORIDC) algorithm. The processing time for each scalable N??N MFMO module...
The software defined radio (SDR) channel simulator is designed and implemented in the FPGA for various wireless communication systems. The dedicated short range communications (DSRC) and ultra-wideband (UWB) channels are carried out to observe the characteristics of multi-path fading channels and validate the correctness of the SDR channel simulator. The hardware reconfiguration of the fading channel...
The hardware reconfiguration feature of a software-defined radio (SDR) architecture can support multiple modes of a digital beamformer (DBF) striving for compactness and efficient processing power, which are important issues for microsatellite synthetic aperture radar (SAR) systems. In this letter, based on the SDR architecture, a DBF system, consisting of multiple beam, direction-of-arrival (DOA)...
The reconfigurable feature of software defined radio (SDR) architecture gives rise to reusability, scalability, and power efficiency. Reusability of hardware supporting multiple modes of DBF strives for compactness and efficient processing power, which are important issue for micro-satellite synthetic aperture radar (SAR) systems. In this paper, according to the SDR architecture, a digital beamforming...
Following the DSRC vehicular communications IEEE802.11p physical layer standards, this paper presents the required computing time estimations of baseband processing modules on the DSP platform and uses this estimation to explain the decision of choosing to implement the 64 point IFFT/FFT module with the FPGA chip. The IFFT/FFT processing time of OFDM modulator/demodulator circuits in applications...
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