The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
DWT has been the main algorithm of image compression, such as in JPEG2000.This paper propose a VLSI structure to perform line-based DWT using lifting scheme. We use this mean to achieve 1D and 2D DWT, examination results show this structure is simple and efficient.
In JPEG2000, 9/7 and 5/3 filters are adopted to realize DWT algorithm. In this paper, we proposed a folded reconfigurable architecture which can be used to 9/7 or 5/3 filter. It is simple and can reduce hardware usage. Further, it is efficient to be used in 2D DWT.
The 4times4 integer transforms are adopted in the MPEG-4 AVC /H.264 standard. In this paper, two novel signal flow graphs of the 4times4 forward and inverse transforms for H.264 are proposed. A new dynamic reconfigurable architecture without using transpose memory for the multiple transforms is proposed on the basis of the new SFGs. Our design is implemented with 0.18 mum CMOS technology. Under a...
Two dimensional discrete wavelet transform (2DDWT) has been adopted as a coding tool of JPEG 2000 image coding and MPEG-4 still texture coding. To make it suitable for real-time image processing applications, it is essential to develop custom VLSI chips for computation of 2D-DWT. A new high efficient architecture is proposed for 2D 1-level DWT, with the feature of original data is scanned by group...
The 4times4 integer transforms are adopted in the MPEG-4 AVC /H.264 standard. In this paper, two novel signal flow graphs of the 4times4 forward and inverse transforms for H.264 are proposed. A high-performance reconfigurable 2-D architecture without using transpose memory for the multiple transforms is proposed on the basis of the new SFGs. Our design is implemented with 0.18 um CMOS technology....
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.