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A 14-bit 2.5-GS/s current-steering digital-to-analog converter (DAC) was designed in a 55-nm CMOS technology. For such a high sampling rate, time-relaxed interleaving digital random return-to-zero (TRI-DRRZ) is an effective method to improve the dynamic performance of the DAC by randomizing the switch glitches. A useful technique called CAL-TRZ is proposed in this paper. It combines TRI-DRRZ with...
In this paper, a 6-bit 320-MS/s successive approximation register analog-to-digital converter (SAR ADC) is presented. The 2-bit/cycle technique and tri-level based charge redistribution technique are utilized to achieve high conversion rate and reduce the hardware cost. The proposed ADC is designed and implemented in a 65-nm CMOS process. Simulation results show that it accomplishes 48.52-dB SFDR,...
A 14-bit 1.0-GS/s current-steering digital-to-analog converter (DAC) was designed in a 65-nm CMOS process. For such current-steering DACs with a high sampling rate, the code-dependent load variations and switching glitches are a main bottleneck which limits the spurious-free dynamic range (SFDR). Dynamic element matching (DEM) has been an effective solution to randomize these glitches for a higher...
This paper proposes a novel complementary current approach to eliminating the code-dependence in the output impedance of current-steering digital-to-analog converters (DACs), and increasing the spurious-free dynamic range (SFDR) significantly. A 14bit 1.0GS/s current-steering DAC design example shows an SFDR increase of 10∼15dB. In traditional designs, one major effect that degrades the linearity...
This paper describes a 10-bit 40 MS/s low power pipelined analog-to-digital converter (ADC). A novel pre-charged fast power-on switched operational amplifier is used to lower power consumption of the pipelined ADC to 13.82 mW. The ADC is designed in a 1.8 V 1P6M 0.18-mum CMOS process. Simulation results indicate that the ADC exhibits Spurious Free Dynamic Range (SFDR) of 74.19 dB and Signal to Noise...
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